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A Low Power Frequency Synthesizer Design for Wireless Power Transfer Applications

AlSuwaidi, Maryam Rashed Obaid
A Master of Science thesis in Electrical Engineering by Maryam Rashed Obaid AlSuwaidi entitled, “A Low Power Frequency Synthesizer Design for Wireless Power Transfer Applications”, submitted in April 2023. Thesis advisor is Dr. Lutfi Albasha and thesis co-advisor is Dr. Hasan Mir. Soft copy is available (Thesis, Completion Certificate, Approval Signatures, and AUS Archives Consent Form).
Wireless power transfer (WPT) is an essential technology for the Internet of Things (IoT) as it enables the deployment of untethered and self-sustaining devices, which eliminates the need for wired power connections. With the increasing number of IoT devices, the demand for wireless charging is also growing, as it can simplify the deployment and maintenance of these devices, reduce the complexity and costs associated with their installation and operation, and allow for the creation of a truly autonomous and ubiquitous network of interconnected devices. A recently developed technique that implements Frequency Diverse Antenna (FDA) beamforming that can localize the power transmission to a desired location has been proposed, yet not verified using actual hardware. The design of a transmitter chip dedicated for FDA-based WPT is of great importance as it will prove the applicability of the FDA technique and will be a critical step towards the realization of the full potential of FDA-based WPT transmitters for IoT and various applications. One of the main blocks of a transmitter chip is the phase-locked loop (PLL), also known as the frequency synthesizer, which provides a clean carrier signal to be used for the up-conversion process. In this context, this thesis aims to design an energy-efficient frequency synthesizer, which can generate a carrier signal of 5.8 GHz, to be implemented in the FDA-based WPT transmitter chip. The total frequency synthesizer system was designed and simulated using Cadence Virtuoso on TSMC 65-nm CMOS technology, where it was able to lock to the desired frequency in 7.7 μsec with a total power consumption of 8.04 mW from a 1 V supply and a VCO phase noise of -114.6 dBc/Hz at 1 MHz offset. The novelty of this work lies in the modularity of the designed PLL structure where it allows for the reusability of all the designed circuits, except the VCO, to be used to generate different frequencies up to 29 GHz. In addition, enhanced performance of the phase frequency detector and divide-by 2 circuits where achieved. This proposed system is considered a future-proof design for future WPT transmitter chips designed at different frequencies.
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