Hammi, OualidAhmed, Serien2023-03-012023-03-012022-1135.232-2022.51http://hdl.handle.net/11073/25170A Master of Science thesis in Electrical Engineering by Serien Ahmed entitled, “Digital Predistortion Using Relaxed Sampling Rates”, submitted in November 2022. Thesis advisor is Dr. Oualid Hammi. Soft copy is available (Thesis, Completion Certificate, Approval Signatures, and AUS Archives Consent Form).Wireless communication's high data rates demands are continuously increasing, thus leading to higher requirements on digital circuits. This leads to complications in the power amplifier's (PA) efficiency and linearity specifications. Accordingly, digital predistortion (DPD) is used to compensate for the nonlinearity of the PA when operating at high-efficiency levels. In DPDs, the bandwidth limitations in the transmitter forward and feedback chains put challenges on the hardware circuits, such as digital to analog converters (DACs) and analog to digital converters (ADCs). This thesis explores the co-existence of relaxed sampling rates in the signal transmit and the signal feedback paths. First, the sampling rate reduction in the feedback path was investigated. The DPD function for this case was extracted using advanced signal processing techniques for constructing the full-rate output from under-sampled measurements. This method was validated in the presence of 20MHz, and 40MHz 5G test signals with several sampling speeds, and the DPD functions were extracted using a twin nonlinear two-box model (RTNTB). Even for an 80% reduction, sufficient linearization capacities were achieved. While a novel predistorter suitable for hybrid implementation was proposed for the transmit path, the distortion function is split into a memory polynomial applied in the baseband domain and an AM/AM only look-up table (LUT) suitable for the RF domain. The hybrid model was compared to benchmark models using 5G test signals with bandwidths of 20MHz and 40MHz and found to provide superior ACLR levels of above 50dBc and a low number of coefficients of 22% less than the benchmarks. The hybrid implementation of the proposed model significantly reduces the speed requirements in the DAC of the transmit path by 70% when compared to conventional DPD systems. Finally, to study the concurrent usage of relaxed sampling rates in both paths, the under-sampled reconstructed output signals were used to build the hybrid predistorter. It was found that a sampling rate reduction of 80% in the feedback path would still provide a 70% reduction of DAC speed in the transmit path while leading to satisfactory linearization performance.en-USPower amplifier (PA)Digital Predistortion (DPD)Behavioral modelingDigital to Analog Converter (DAC)Analog to Digital Converter (ADC)ResamplingHybrid predistorterThesis